The subject of this invention is a method and an apparatus for a conversion of a value of an analog signal to a compressed digital word that can be applied in monitoring and control systems.
A conversion of a voltage value to a linear digital word using a successive approximation scheme is known from the article James McCreary, Paul R. Gray “A High-Speed, All-MOS Successive-Approximation Weighted Capacitor A/D Conversion Technique”, IEEE International Solid-State Circuits Conference, Feb. 12, 1975, pp. 38-39. The solution according to the aforementioned article uses a technique of charge redistribution among a number of m+1 capacitors, while m is a number of bits in the linear digital word. The capacitances of the capacitors are binary-weighted except the last capacitor whose capacitance is the same as the capacitance of the second-to-last capacitor. In the first stage of conversion, an input voltage is sampled which causes an accumulation of a charge portion in the capacitors that are connected in parallel to the input voltage, while the charge portion accumulated in the capacitors is proportional to a value of the input voltage. The accumulated charge portion is further redistributed among the capacitors by searching such a combination of capacitors connected in parallel that a voltage created on these capacitors by redistributed charge is as close to a given reference voltage as possible. At each conversion step, a capacitor which is connected to a set of capacitors has lower capacitance compared to a capacitor connected in a previous step. If a voltage created on the set of capacitors is higher than the reference voltage, the actually connected capacitor is kept connected to the set of capacitors in next steps, and a corresponding output bit is evaluated to one. Otherwise, the actually connected capacitor is disconnected from the set of capacitors, and a corresponding output bit is evaluated to zero.
A method of representation of a value of analog signal by a compressed digital word according to A law is known from the document ITU-T G.711 “Pulse code modulation of voice frequencies”. A full scale input range for positive signal values and a full scale input range for negative signal values of the analog-to-digital converter are split into eight unequal sections. The sections no. 7 correspond to upper halves of the full scale input range for absolute negative and positive values of the analog-to-digital converter. Each section of a lower index corresponds to upper halves of remaining parts of full scale input range except the section no. 0 whose range is the same as the range of the section no. 1. Each section is split into 16 quantization steps. The most significant bit of a compressed digital word according to A law represents a sign of a value of input signal. The next 3 bits represent an index of a section to which the value of input signal corresponds. The 4 least significant bits of the compressed digital word according to A law represents an index of a quantization step to which the value of input signal corresponds.
A method for conversion of a voltage value to a compressed digital word according to successive approximation scheme is known from the article Eberhard Pfrenger, Peter Picard and Frithjof von Sichart “A Companding D/A Converter for a Dual-Channel PCM CODEC”, IEEE International Solid-State Circuits Conference, Feb. 16, 1978, pp. 186-187. Bits of the n-bit compressed digital word are evaluated successively by the use of a successive approximation register (SAR) starting from the most significant bit. In each step, a tested bit is set to one and provided via an expander to an input of m-bit linear digital-to-analog converter in order to create an approximation of the converted value of the analog input signal. If the created approximation is higher than the value of analog input signal, then the corresponding output bit is set to zero. Otherwise, output bit is set to one. The number of conversion steps is not lower than n+1 and independent of the value of the analog input signal.
An apparatus for conversion of a voltage value to a linear digital word according to successive approximation scheme is known from the article James McCreary, Paul R. Gray “A High-Speed, All-MOS Successive-Approximation Weighted Capacitor A/D Conversion Technique”, Proceedings of IEEE International Solid-State Circuits Conference, February 1975, pp. 38-39. The aforementioned apparatus comprises a successive approximation capacitor array whose one input is connected to a source of converted input voltage, whereas the other input is connected to a source of the reference voltage while its output is connected to a control module through a comparator. The control module is equipped with a digital output and an input of the clock signal that clocks a conversion process. Two control outputs of the control module are connected to the comparator, and the other control outputs of the control module are connected to the successive approximation capacitor array.
The successive approximation capacitor array comprises a number of n capacitors of binary-weighted capacitances and an additional capacitor while the first plate of each capacitor in the array is connected to the first common rail, and the capacitance of the additional capacitor equals the capacitance of the smallest capacitor in the array. The other plates of the capacitors in the array are connected to the other common rail through the change-over switches whose other stationary contacts are connected to the ground of the circuit. The first common rail is connected to the non-inverting input of the comparator, and the second common rail is connected through another switch to the source of the input voltage or to the source of the reference voltage, while the inverting input of the comparator is connected to the ground of the circuit.
Method and apparatus for conversion of a time interval to a digital word is known from the patent document U.S. Pat. No. 9,063,518. The apparatus comprises an array of capacitors whose control inputs are connected to a set of control outputs of a control module. The control module is equipped with a digital output, a complete conversion signal output, a trigger input and two control inputs. The first control input is connected to the output of the first comparator whose inputs are connected to one pair of outputs of the array of capacitors, and the other control input of the control module is connected to the output of the second comparator whose inputs are connected to the other pair of outputs of the array. Besides, the source of auxiliary voltage together with the source of the reference voltage, the sampling capacitor, and two controlled current sources are connected to the set of capacitors while control inputs of both current sources are connected to control outputs of the control module.
An apparatus for conversion of a voltage value to a compressed digital word according to successive approximation scheme is known from the article Eberhard Pfrenger, Peter Picard and Frithjof von Sichart “A Companding D/A Converter for a Dual-Channel PCM CODEC”, IEEE International Solid-State Circuits Conference, Feb. 16, 1978, pp. 186-187. The aforementioned apparatus comprises a comparator whose non-inverting input is used to provide an analog input signal. A comparator output is connected to an input of successive approximation register SAR comprising n-bit digital output, which is used to output a compressed digital word. This output is connected to n-bit input of an expander whose m-bit output of a linear digital-to-analog converter. A converter output is connected to an inverting input of the comparator.